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document number: mc33660 rev 5.0, 10/2013 freescale semiconductor ? advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? ? freescale semiconductor, inc., 2011-2013. all rights reserved. iso k line serial link interface the 33660 is a serial link bus interface device designed to provide bi-directional half-duplex communication interfacing in automotive diagnostic applications. it is designed to interface between the vehicle?s on-board microcontroller, and systems off-board the vehicle via the special iso k line. the 33660 is designed to meet the diagnostic systems iso9141 specif ication. the device?s k line bus driver?s output is fully protec ted against bus shorts and over- temperature conditions. the 33660 derives its robustness to temperature and voltage extremes by being built on a sm artmos process, incorporating cmos logic, bipolar/mos analog circuitry, and dmos power fets. although the 33660 was principally designed for automotive applications, it is suited for other serial commun ication applications. it is parametrically specified over an ambient temperature range of ? -40 oc ? t a ? 125 oc and 8.0 v ? v bb ? 18 v supply. the economical so-8 surface-mount plastic package makes the 33660 very cost effective. features ? operates over wide supply voltage of 8.0 to 18 v ? operating temperature of -40 to 125 ? c ? interfaces directly to st andard cmos microprocessors ? iso k line pin protected against shorts to battery ? thermal shutdown with hysteresis ? iso k line pin capable of high currents ? iso k line can be driven with up to 10 nf of parasitic capacitance ?8.0 kv esd protection attainable with few additional components ? standby mode: no v bat current drain with v dd at 5.0 v ? low current drain during operation with v dd at 5.0 v figure 1. 33660 simplified application diagram iso9141 physical interface ef suffix (pb-free) 98asb42564b 8-pin soicn 33660 ordering information device (for tape and reel orders, add an r2 suffix) temperature range (t a ) package mc33660ef -40 to 125 c 8-soicn mc33660bef vdd iso k-line t x d r x d vdd v dd rx tx gnd iso cen vbb mcu 33660 dx scirxd scitxd +v bat
analog integrated circuit device data ? 2 freescale semiconductor 33660 device variations device variations table 1. device variations parameter symbol condition 33660 33660b (1) vbb load dump peak voltage (in accordance with iso 7637-2 & iso 7637-3) v bb(5a) v bb(5b) pulse 5a ? 470 ohm series resistor and 100 nf capacitor to gnd on vbb pulse 5b ? 470 ohm series resistor and 100 nf capacitor to gnd on vbb ? 45 v 82 v 45 v module level esd (air discharge, powered) (6) v esd4 33 v zener diode and 470 pf capacitor to gnd on iso ? 25000 v notes 1. recommended for all new designs
analog integrated circuit device data ? freescale semiconductor 3 33660 internal block diagram internal block diagram figure 2. 33660 simplified internal block diagram thermal shutdown vbb 60 v cen 10 v 125 k ? r hys 10 v 45 v rx iso vdd tx 55 v 125 k ? gnd master bias 10 v 10 v 600 k ? 55 k ? 550 k ? 110 k ? 2.0 k ? 20 v 3.0 k ? * only applies to 33660b
analog integrated circuit device data ? 4 freescale semiconductor 33660 pin connections pin connections figure 3. 33660 pin connections table 2. 33660 pin definitions pin number pin name definition 1 vbb battery power through external resistor and diode. 2 nc not to be connected. (2) 3 gnd common signal and power return. 4 iso bus connection. 5 tx logic level input for data to be transmitted on the bus. 6 rx logic output of data received on the bus. 7 vdd logic power source input. 8 cen chip enable. logic ?1? for active state. logic ?0? for sleep state. notes 2. nc pins should not have any connections made to them. nc pins are not guaranteed to be open circuits. 2 3 4 8 7 6 5 1 1 2 4 3 8 7 5 6 cen vdd tx vbb nc gnd iso rx
analog integrated circuit device data ? freescale semiconductor 5 33660 electrical characteristics maximum ratings electrical characteristics maximum ratings table 3. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. rating symbol value unit vdd dc supply voltage v dd -0.3 to 7.0 v vbb load dump peak voltage (in accordance with iso 7637-2 & iso 7637-3) pulse 5a - 33660b only pulse 5b v bb(5a) v bb(5b) 82 45 v iso pin load dump peak voltage (3) v iso 40 v esd voltage (4) human body model (5) machine model (5) 33660 33660b charge device model (5) corner pins all other pins module level esd (air discharge, powered) (6) 33660b only iso pin with 33 v zener diode and 470 pf capacitor to gnd - v esd1 v esd2 v esd3-1 v esd3-2 v esd4 2000 150 200 750 500 25000 v iso clamp energy (7) e clamp 10 mj storage temperature t stg -55 to +150 ? c operating case temperature t c -40 to +125 ? c operating junction temperature t j -40 to +150 ? c power dissipation t a = 25 ? c p d 100 mw peak package reflow temperature during reflow (8) , (9) t pprt note 9. c thermal resistance: junction-to-ambient r ? ja 150 ? c/w notes 3. device will survive double battery jump start conditions in typica l applications for 10 minutes duration, but is not guarante ed to remain within specified parametric limits during this duration. 4. esd data available upon request. 5. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ), esd2 testing is performed in accordance with the machine model (c zap = 200 pf, r zap = 0 ? ), esd3 testing is performed in accordance with the charge device model (c zap = 4.0 pf). 6. esd4 testing is performed in accor dance with iso 10605 esd model (c = 330 pf, r = 2.0 k ? ). esd discharges start at 5.0 kv and go up to 25 kv in increments of 5.0 kv. there are two positions for discharges: 8.0 cm cable from iso connector, 85 cm cable from iso connector. there are 10 esd discharges per vo ltage at each cable position at a minimum of 1.0 s intervals. remaining charge is not bled off after every discharge. 7. nonrepetitive clamping capability at 25 ? c. 8. pin soldering temperature limit is for 10 seconds maximum duration. not designed fo r immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 9. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. (i.e. mc33xxxd enter 33xxx), and review parametrics.
analog integrated circuit device data ? 6 freescale semiconductor 33660 electrical characteristics static electrical characteristics static electrical characteristics table 4. static electrical characteristics characteristics noted under conditions of 4.75 v ? v dd ? ? 5.25 v, 8.0 v ? v bb ? 18 v, -40 ? c ? t c ? 125 ? c, unless otherwise noted. characteristic symbol min typ max unit power and control v dd sleep state current t x = 0.8 v dd , cen = 0.3 v dd i dd(ss) ? ? 0.1 ma v dd quiescent operating current t x = 0.2 v dd , cen = 0.7 v dd i dd(q) ? ? 1.0 ma v bb sleep state current v bb = 16 v, t x = 0.8 v dd , cen = 0.3 v dd i bb(ss) ? ? 50 a v bb quiescent operating current t x = 0.2 v dd , cen = 0.7 v dd i bb(q) ? ? 1.0 ma chip enable input high voltage threshold (10) input low voltage threshold (11) v ih(cen) v il(cen) 0.7 v dd ? ? ? ? 0.3 v dd v chip enable pull-down current (12) i pd(cen) 2.0 ? 40 a t x input low voltage threshold r iso = 510 ? (13) v il(tx) ? ? 0.3 x v dd v t x input high voltage threshold r iso = 510 ? (14) v ih(tx) 0.7 x v dd ? ? v t x pull-up current (15) i pu(tx) -40 ? -2.0 a r x output low voltage threshold r iso = 510 ? , t x = 0.2 v dd , r x sinking 1.0 ma v ol(rx) ? ? 0.2 v dd v r x output high voltage threshold r iso = 510 ? , t x = 0.8 v dd , r x sourcing 250 a v oh(rx) 0.8 v dd ? ? v thermal shutdown (16) t lim 150 170 ? ? c notes 10. when i bb transitions to >100 a. 11. when i bb transitions to <100 a. 12. enable pin has an internal current pull-down. pu ll-down current is measured with cen pin at 0.3 v dd . 13. measured by ramping t x down from 0.8 v dd and noting t x value at which iso falls below 0.2 v bb . 14. measured by ramping t x up from 0.2 v dd and noting the value at which iso rises above 0.9 v bb . 15. t x pin has internal current pull-up. pull-up current is measured with t x pin at 0.7 v dd . 16. thermal shutdown performance (t lim ) is guaranteed by design, but not production tested .
analog integrated circuit device data ? freescale semiconductor 7 33660 electrical characteristics static electrical characteristics table 3. static electrical characteristics (continued) characteristics noted under conditions of 4.75 v ? v dd ? ? 5.25 v, 8.0 v ? v bb ? 18 v, -40 ? c ? t c ? 125 ? c, unless otherwise noted. characteristic symbol min typ max unit iso i/o input low voltage threshold r iso = 510 ? , t x = 0.8 v dd v il(iso) ? ? 0.4 x v bb v input high voltage threshold r iso = 510 ? , t x = 0.8 v dd v ih(iso) 0.7 x v bb ? ? v input voltage hysteresis v hys(iso) 0.05 x v bb ? 0.1 x v bb v internal pull-up current r iso = ? ? , t x = 0.8 v dd , v iso = 9.0 v, v bb = 18 v i pu(iso) -5.0 ? -140 a short-circuit current limit r iso = 0 ? , t x = 0.4 v dd , v iso = v bb i sc(iso) 50 ? 200 ma output low voltage r iso = 510 ? , t x = 0.2 v dd v ol(iso) ? ? 0.1 x v bb v output high voltage r iso = ? ? , t x = 0.8 v dd v oh(iso) 0.95 x v bb ? ? v
analog integrated circuit device data ? 8 freescale semiconductor 33660 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted und er conditions of 4.75 v ? v dd ? ? 5.25 v, 8.0 v ? v bb ? 18 v, -40 ? c ? t c ? 125 ? c, unless otherwise noted. characteristic symbol min typ max unit fall time (17) r iso = 510 ? to v bb , c iso = 10 nf to ground t fall(iso) ? ? 2.0 s iso propagation delay (18) high to low: r iso = 510 ? , c iso = 500 pf (19) low to high: r iso = 510 ? , c iso = 500 pf (20) t pd(iso) ? ? ? ? 2.0 2.0 s notes 17. time required iso voltage to transition from 0.8 v bb to 0.2 v bb . 18. changes in the value of c iso affect the rise and fall time but have minimal effect on propagation delay. 19. step t x voltage from 0.8 v dd to 0.2 v dd . time measured from v ih(tx) until v iso reaches 0.3 v bb . 20. step t x voltage from 0.2 v dd to 0.8 v dd . time measured from v il(tx) until v iso reaches 0.7 v bb .
analog integrated circuit device data ? freescale semiconductor 9 33660 electrical characteristics electrical performance curves electrical per formance curves figure 4. iso input threshold/v bb vs. temperature figure 5. iso output/v bb vs. temperature figure 6. iso fall time vs. temperature figure 7. iso propagation delay vs. temperature -50 0 50 100 150 0.475 0.5 0.525 0.55 0.575 0.6 t a , ambient temperature ( ? c) v ih ; v dd = 5.25 v, v bb = 18 v v ih ; v dd = 4.75 v, v bb = 8.0 v v il ; v dd = 5.25 v, v bb = 18 v v il ; v dd = 4.75 v, v bb = 8.0 v v il and v ih , input threshold (ratio) -50 0 50 100 150 t a , ambient temperature ( ? c) 0.65 0.7 0.75 0.8 0.85 0.9 0.95 v dd = 5.25 v, v bb = 18 v v dd = 4.75 v, v bb = 8.0 v t fall(iso) , iso fall time ( s) v oh v ol t a , ambient temperature ( ? c) -50 0 50 100 150 0 0.2 0.4 0.6 0.8 1.0 1.2 v dd = 4.75 v, v bb = 8.0 v and v dd = 5.25 v, v bb = 18 v v ol and v oh , iso output (ratio) -50 0 50 100 150 t a , ambient temperature ( ? c) 0.2 0.3 0.4 0.5 0.6 0.7 pd h-l pd l-h v dd = 5.25 v, v bb = 18 v v dd = 4.75 v, v bb = 8.0 v v dd = 4.75 v, v bb = 8.0 v v dd = 5.25 v, v bb = 18 v t pd(iso) , propagation delay ( s)
analog integrated circuit device data ? 10 freescale semiconductor 33660 typical applications introduction typical applications introduction the 33660 is a serial link bus interface device conforming to the iso 9141 physical bus specification. the device is designed for automotive envir onment usage, compliant with on-board diagnostics (obd) requirements set forth by the california air resources board (carb) using the iso k line. the device does not incorporate an iso l line. it provides bi- directional half-duplex commun ications interfacing from a microcontroller to the communication bus. the 33660 incorporates circuitry to interface the digital translations from 5.0 v microcontroller logic levels to battery level logic, and from battery level logic to 5.0 v logic levels. the 33660 is built using freescale semiconductor?s smartmos process and is packaged in an 8-pin plastic soic. functional description the 33660 transforms 5.0 v microcontroller logic signals to battery level logic signals and visa versa. the maximum data rate is set by the rise and fa ll time. the fall time is set by the output driver. the rise time is set by the bus capacitance and the pull-up resistors on the bus. the fall time of the 33660 allows data rates up to 150 kbps using a 30 percent maximum bit time tran sition value. the serial link interface will remain fully functional over a battery voltage range of 6.0 to 18 v. the device is parametrically specified over a dynamic v bb voltage range of 8.0 to 18 v. required input levels from the microcontroller are ratio- metric with the v dd voltage normally used to power the microcontroller. this enhances the 33660?s ability to remain in harmony with the r x and t x control input signals of the microcontroller. the r x and t x control inputs are compatible with standard 5.0 v cmos circuitry. for fault tolerant purposes the t x input from the microcontroller has an internal passive pull-up to v dd , while the cen input has an internal passive pull-down to ground. a pull-up to battery is internally provided as well as an active data pull-down. the internal active pull-down is current-limit protected against shorts to battery, and further protected by thermal shutdown . typical applications have reverse battery protection by the incorporation of an external 510 ? pull-up resistor and a diode to battery. reverse battery protection of the device is provided by the use of a reverse battery blocking diode (see ?d? in the typical application diagram on page 10 ). battery line transient protection of the device is provided for by using a 45 v zener and a 500 ? resistor connected to the v bb source, as shown in the same diagram. device esd protection from the communication lines exiting the module is through the use of the capacitor connected to the v bb device pin, and the capacitor used in conjunction with the 27 v zener connected to the iso pin. figure 8. typical application diagram components necessary for reverse battery (1 ), overvoltage transient (2), and 8.0 kv esd protection (3) in a metal module case. v cc d x scir x d scit x d mcu vdd cen rx tx vbb iso gnd 500 ? (2) d(1) iso k line 510 ? service scan tool or end of production line programming or system checking t x d r x d +v dd = 5.0 v 45 v(2) 27 v(3) 5.0 nf(3) 33660 1.0 nf 10 nf(3) +v bat on-board diagnostic link
analog integrated circuit device data ? freescale semiconductor 11 33660 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. ef suffix (pb-free) 8-pin 98asb42564b rev. v
analog integrated circuit device data ? 12 freescale semiconductor 33660 packaging package dimensions ef suffix (pb-free) 8-pin 98asb42564b rev. v
analog integrated circuit device data ? freescale semiconductor 13 33660 revision history revision history revision date description of changes 1.0 1/2011 ? initial release 2.0 9/2011 ? adjusted format to meet current compliance standards. no data was altered. 3.0 10/2011 ? updated the pc part number to mc. 4.0 2/2013 ? added pc33660bef to the ordering information ? redefined vbb load dump peak voltage (in accordance with iso 7637-2 & iso 7637- 3) for the 33660b ? added module level esd (air discharge, powered) (6) for the 33660b ? added note (6) ? increased esd structure voltage for 33660b, and added bleed-off circuit on vbb pin in figure 2 5.0 10/2013 ? clarified machine model limits for mc33660 and mc33660b, page 5
document number: mc33660 rev 5.0 10/2013 information in this document is provided solely to enable sys tem and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. freescale reserves the right to make changes without fu rther notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or s pecifications can and do vary in diff erent applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditi ons of sale, which can be found at the following address: freescale.com/salestermsandconditions . freescale and the freescale logo are trademarks of fr eescale semiconductor, inc., reg. u.s. pat. & tm. off.smartmos is a trademark of freescale semiconductor, in c. all other product or service names are the property of their respective owners. ? 2013 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support

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